The present invention relates to an SOI (silicon-on insulator) substrate manufacturing method and, more particularly, to an SOI manufacturing method which significantly decreases warpage in the SOI substrate.
In general, a silicon substrate is widely used in the fabrication of semiconductor devices. However, silicon substrate based devices suffer from several problems.
First, use of a silicon substrate makes shallow junction-formation in source and drain regions of a transistor difficult. This problem is an obstacle to the realization more highly integrated semiconductor devices. This problem also precludes reduction of the parasitic junction capacitance apparent in the silicon substrate between source and drain regions of the transistor. These disabilities make further improvement in the electrical performance characteristics of the semiconductor device difficult, and in particular impair advances in operating speed.
Second, semiconductor devices typically include a well within the silicon substrate which accommodates a transistor cell, or other active device. Such structures result in soft-error rate (SER) difficulties.
Third, fabrication of semiconductor devices having CMOS transistors formed in a silicon substrate gives rise to the latch-up phenomenon.
Since semiconductor devices manufactured with silicon substrates exhibit these problems, there is an increasing tendency to replacing the silicon substrate with a SOI substrate. Use of a SOI substrate in the fabrication of a semiconductor device overcomes many of these problems. These improvements can generally be attributed to the structure of the SOI substrate which includes an oxidized layer, a supporting substrate below the oxidized layer and a semiconductor layer having a thickness of 0.5 .mu.m or less overlaying the oxidized layer.
More particularly, since the thickness of the semiconductor layer corresponds to the junction depth of the source and drain regions, a thin junction can readily be obtained by adjusting the thickness of the semiconductor layer. In addition, the respective bottoms of the source and drain regions contact the oxidized layer, thus decreasing the parasitic junction capacitance. This improvement contributes to increases in the operating speed of the semiconductor device. Full isolation of active devices such as a transistor by an insulating layer can also be achieved by use of a SOI substrate. Full isolation entirely eliminates the latch-up problem inherent in CMOS structures formed in silicon substrates.
FIGS. 1A and 1B are cross-sectional views which illustrate a manufacturing method for a conventional SOI substrate. FIG. 1A shows the bonding of a supporting substrate 10 with a semiconductor substrate 14. The bonding step is performed by forming an oxidized layer 12 on one surface of supporting substrate 10 or on one surface of semiconductor substrate 14, and thereafter bonding supporting substrate 10 and semiconductor substrate 14 by using oxidized layer 12 as the bonding medium. Here, a silicon wafer is widely used for semiconductor substrate 14, and the bonding of supporting substrate 10 and semiconductor substrate 14 is accomplished by use of a high temperature oxidation method, and an electrostatic bonding method, or a method of thermal processing at high temperature in a nitrogen atmosphere.
FIG. 1B shows the completion of the SOI substrate. The completion of the SOI substrate is accomplished by removing an upper portion of semiconductor substrate 14 using a grinding process, and a CMP (chemical-mechanical polishing) process to remove an upper portion of the semiconductor substrate 14 and obtain a finished semiconductor layer 14 a having a desired thickness.
Unfortunately, the grinding process stresses semiconductor substrate 14. More particularly, use of a silicon wafer as semiconductor substrate 14 produces a compressive stress (S.sub.F) on the front surface of a SOI substrate. Accordingly, as illustrated by the difference between FIG. 1A and FIG. 1B, SOI substrate 12 warps under the compressive stress of the grinding/polishing processes resulting in an irregular thickness for finished semiconductor layer 14a. During subsequent semiconductor processing such as photolithography processing steps, the warped semiconductor layer 14a makes mask alignment difficult, The warped semiconductor substrate also gives rise to additional stresses thermal processing steps. Such adverse effects may result in the lifting of the semiconductor substrate from SOI substrate.